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GPIO ICs Series
GPIO Expander IC
BU1850MUV
No.09098EAT02
Description GPIO expander is useful especially for the application that is in short of IO ports. It can 2 1. Control GPIO output states by I C write protocol. 2 2. Know GPIO input states by I C read protocol. Furthermore,it has the interrupt function that can release CPU from polling the registers in the GPIO expander. GPIO expander are also equipped with Built-in power on reset, 3V tolerant input,and NMOS open-drain output. Features 1) An 8-Port General purpose input/output interface 150kPull-down resistance. 2) NMOS Open-drain output interrupt controller with up to 1us pulse noise filter and bit mask function for individual GPIO port. 3) 3volt tolerant Input 4) Built-in Power On Reset 5) 3mmx3mm small package Absolute maximum ratings o (Ta=25 C) Parameter Supply Voltage*1 Symbol VDD VDDIO VI Input voltage VIT Storage temperature range Package power
This IC is not designed to be X-ray proof.
Rating -0.3 ~ +4.5 -0.3 ~ +4.5 -0.3 ~ VDD +0.3 -0.3 ~ 4.5 -55 ~ +125 272*2
*1
Unit V V V V mW
comment VDDVDDIO
XRST, ADR XINT, SCL, SDA, GPIO[7:0]
Tstg PD
*1 *2
It is prohibited to exceed the absolute maximum ratings even including +0.3 V. o o Package dissipation will be reduced each 2.72mW/ C when the ambient temperature increases beyond 25 C.
Operating conditions Parameter Supply voltage range (VDD) Supply voltage range (VDDIO) Symbol VVDD VVDDIO VIN Input voltage range VINT Operating temperature range I2C operating frequency Topr FI2C -0.2 -30 3.6 +85 400 V kHz Slave Min 1.65 1.65 -0.2 Typ 1.80 1.80 Max 3.6 3.6 VVDD+0.2 Unit V V V Conditions Core, XINT, XRST, SCL, SDA, ADR, Power On Reset GPIO[7:0] XRST, ADR XINT, SCL, SDA, GPIO[7:0]
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Package Specification
Technical Note
BU1 850
Lot No .
(UNIT: mm)
Fig.1 Package Specification (VQFN016V3030)
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Pin Assignment
Technical Note
12 GPIO3
11 GPIO2
10 GPIO1
13 GPIO4 14 GPIO5 15 GPIO6 16 GPIO7
9 GPIO0
8 VSS 7 VDDIO 6 VDD 5 SDA
2 XRST
1 XINT
Fig.2 Pin Diagram (Top View)
Block Diagram
Functional Block Diagram
XINT Interrupt Filter Interrupt Logic INT_MASK IN/OUT Control
VDD
ADR Shift Register GPIO [7:0]
4 ADR
3 SCL
VDDIO
8bit 8bit
SCL SDA
Power On Reset
Input Filter
I2C Bus Control
GPIO[7:0]
XRST VSS
Reset Gen
Write Pulse Read Pulse
Fig.3 Functional Block Diagram
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Pin-out Functional Descriptions
Technical Note
PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
*1 *2 *3
PIN name XINT XRST SCL ADR SDA VDD VDDIO VSS GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7
I/O O I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O
Power source system VDD VDD VDD VDD VDD VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO
Function Interrupt signal (1s pulse cut)*1 (NMOS Open-drain) ResetLow Active Clock for I C Select device address of I C Serial data inout for I C (NMOS Open-drain) Power supply (Core, I/O, Power On Reset) Power supply (I/O) GND
2 2 2
Init Hi-Z I I I Hi-Z -
Cell Type B E A E C -
General purpose input/output. *2 (NMOS Open-drain /CMOS Output, *3 150kPull-down )
I Pull-down
D
Specific bit mask control is decided by internal register value. Pull-up more than VDDIO voltage. It is possible to select Pull-down ON or OFF with register.
A
B
C
D
E
Fig.4 Equivalent IO circuit diagram
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Technical Note
Functional Description 1. Power Modes The device enters the state of Power Down when XRST="Low" or enters the operation state when XRST=High after powered. Refer to "Electrical Specification" section 5 for a detailed startup sequence. 1-1 Power supply A single supply to Core power supply (VDD) and IO power supply (VDDIO) is prohibited. Supply the power supply to the Core power supply and the IO power supply at the same time. 1-2 Power On Reset A Power On Reset logic is implemented in this device. Therefore, it will operate correctly even if the XRST port is not used. In this case, the XRST port must be connected to high(VDD). 1-3 State of Power Down 2 The device enters the state of Power Down by XRST="Low". An internal circuit is initialized and I C interface is invalid is input. Power On Reset becomes inactive during this state. 1-4 State of operation The device enters the operation state by setting XRST to "High". The I2C interface starts communication is the START condition. It becomes standby by the STOP condition. Power On Reset is active in this state.
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2.
2
Technical Note
I C Bus Interface Each function of GPIO is controlled by an internal register. The I2C Slave interface is used to write or read this internal register. The device supports up to 400kHz Fast-mode data transfer rate. 2-1 Slave address Two device addresses (Slave address) can be selected by ADR port.
A7 ADR=0 ADR=1
2-2
A6 0 0
A5 0 0
A4 1 1
A3 0 1
A2 0 1
A1 1
R/W 1/0
0 0
0
Data transfer One bit of data is transferred during SCL = "1". During the bit transfer SCL = "1" cycle, the signal SDA should keep the value. If SDA changes during SCL = "1", a START condition or STOP condition occur and it is interpreted as a control signal.
SDA SCL Data is valid when SDA is stable SDA is variable
Fig.5 Data transfer
2-3 START-STOP-Repeated START conditions When SDA and SCL are "1", the data isn't transferred on the 2-wire bus. If SCL remains "1" and SDA transfers from "1" to "0", it means a "Start condition" is occurred and access is started. If SCL remains "1" and SDA transfers from "0" to "1", it means a "Stop condition" is occurred and access is stopped. It becomes repeated START condition (Sr) the START condition enters again although the STOP condition is not done.
SDA SCL
S
Sr Repeated START Condition Fig.6 START-STOP-Repeated START conditions
P STOP Condition
START Condition
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Technical Note
2-4 Acknowledge After start condition is occurred, 8 bits data will be transferred. SDA is latched by the rising edge of SCL. Then the "Master" opens SDA to "1" and "Slave" de-asserts SDA to "0" as an "Acknowledge" returned.
Fig.7 Acknowledge 2-5 Writing protocol Register address is transferred after one byte of slave address with R/W bit. The 3rd byte data is written to internal register which defined by the 2nd byte. However, when the register address increased to the final address (13h), it will be reset to (00h) after the byte transfer.
S X X X X X X X 0 A X X X A4 A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 A
Slave address R/W=0(write) Register address data Register address increment A=acknowledge A=not acknowledge S=Start condition P=Stop condition
D7 D6 D5 D4 D3 D2 D1 D0 A P
data Register address increment
Transmit from master
Transmit from slave
Fig.8 Writing protocol
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Technical Note
2-6 Reading protocol After Writing the slave address and Read/Write commend bits, the next byte is read. The reading register address is next of previous accessed address. Therefore, the data is read with address increment. When the address in increased to the last, the following read address will be reset to (00h).
Fig.9 Readout protocol 2-7 Complex reading protocol After the specifying the internal register address, a repeated START condition occurs and the direction of data transfer is changed then reading access is done. Therefore, the data is read followed by address increment. If the address is increased to the last, it will be reset to (00h).
S X X X X X X X 0 A X X X A4 A3 A2 A1 A0 A Sr X X X X X X X 1 A
Slave address R/W=0(write) Register address Slave address R/W=1(read)
D7 D6 D5 D4 D3 D2 D1 D0 A
data Register address increment
D7 D6 D5 D4 D3 D2 D1 D0 A P
data Register address increment A=acknowledge A=not aclnowledge S=Start condition P=Stop condition Sr=Repeated Start condition
Transmit from master
Transmit from slave
Fig.10 Complex reading protocol 2-8 Illegal access of I2C The data accessed at that time is annulled, and access it again. The illegal accesses are as follows. The START condition and the STOP condition are continuously generated. When the Slave address and the R/W bit is written, repeated START condition and the STOP condition are generated. Repeated START condition and the STOP condition are generated while writing data.
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3. Register configuration The address is increased one by one when data is continuously written. When the final address is set to 13h, then the next address 00h will be written. By making XRST "Low", the setting register value will be initialed shown in following register map. 3-1 Register map
Addr 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h
Technical Note
Init 00h 00h 00h 00h 00h 00h
Type R/W R/W R R/W R/W R/W
D7
reserved reserved reserved reserved RESET reserved reserved reserved INTEN7 reserved reserved reserved reserved reserved reserved reserved GPI7 GPO7 WRSEL7 XPD7
D6
reserved reserved reserved reserved reserved reserved reserved reserved INTEN6 reserved reserved reserved reserved reserved reserved reserved GPI6 GPO6 WRSEL6 XPD6
D5
reserved reserved reserved reserved reserved reserved reserved reserved INTEN5 reserved reserved reserved reserved reserved reserved reserved GPI5 GPO5 WRSEL5 XPD5
D4
reserved reserved reserved reserved reserved reserved reserved reserved INTEN4 reserved reserved reserved reserved reserved reserved reserved GPI4 GPO4 WRSEL4 XPD4
D3
reserved reserved reserved reserved reserved reserved reserved reserved INTEN3 reserved reserved reserved reserved reserved reserved reserved GPI3 GPO3 WRSEL3 XPD3
D2
reserved reserved reserved reserved reserved reserved reserved reserved INTEN2 reserved reserved reserved reserved reserved reserved reserved GPI2 GPO2 WRSEL2 XPD2
D1
reserved reserved reserved reserved reserved reserved reserved reserved INTEN1 reserved reserved reserved reserved reserved reserved reserved GPI1 GPO1 WRSEL1 XPD1
D0
reserved reserved reserved reserved reserved reserved reserved reserved INTEN0 reserved reserved reserved reserved reserved reserved reserved GPI0 GPO0 WRSEL0 XPD0
Do not write reserved resisters excluding "0". 10h address register is disregarded even if it is written.
3-2 Resister function
n is the number of GPIO[7:0] ports.
Symbol RESET INTENn GPIn GPOn WRSELn XPDn
Addr 04h 08h 10h 11h 12h 13h
Description The register is returned to an initial value by writing "1". This register value is returned to "0". GPIn register is not initialized. Interrupt of GPIOn port is enabled by "1". It is masked by "0". Read GPIOn port. Writing is disregarded. Output value of GPIOn port. GPIOn port is input by "0" and output by "1". Pull-down of GPIOn port is on by "0" and off by "1". GPIOn should be input.
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4. GPIO-Interrupt 4-1 GPIO configuration As the default value, GPIO[7:0] ports are input and Pull-down. At this time, WRSELn is "0" and XPDn is "0". (n is the number of GPIO[7:0] ports.)
Technical Note
Refer to the following for the configuration of GPIO. Register State of GPIO GPOn Input, Pull-down ON Input, Pull-down OFF Output, H drive Output, L drive Output, Hi-Z -1
1
WRSELn 0 0 1 1 0
XPDn 0 1 * * 1
* * 1 0 0
1
Make external Pull-up the terminal potential which is the potential of VVDDIO or more.
About GPIO port not used When making it to the output, open it. When making it to the input, do not open it. It is forced by "0" or Pull-down on. When interrupt is enabled, mask INTEN register in which the port is not used to "0".
4-2 Interrupt configuration When interrupt is generated, L is output from XINT port. The default value is Hi-Z. Make it Pull-up. For the default value, interrupt is masked with INTEN register "0". The bit to be used is made "1", and the mask is released. WRSEL register should be "0"(input). 4-3 Write to GPIO port After setting the internal register address, the data from master is written from MSB. After Acknowledge is returned, the value of each GPIO port will be changed. When the register is written, Write Configuration Pulse is generated according to the timing of Acknowledge.
SCL
1
2
3
4
5
6
7
8
9
SDA
S
X
X
X
X
X
X
X
0
Ack
MSB
Reg Address
LSB
Ack
MSB
Data1 (GPO[7:0])
LSB
Ack
P
Start Condition Write Configuration Pulse GPIO[7:0]
Write
Acknowledge From Slave
Acknowledge From Slave Stop Condition
Data1 Valid
tDV
SCL
1
2
3
4
5
6
7
8
9
SDA
S
X
X
X
X
X
X
X
0
Ack
MSB
Reg Address
LSB
Ack
MSB
Data1 (GPO[7:0])
LSB
Ack
MSB
WRSEL = Write Mode
LSB
Ack
P
Start Condition Write Configuration Pulse GPIO[7:0]
Write
Acknowledge From Slave
Acknowledge From Slave
Acknowledge From Slave Stop Condition
Data1 Valid
tDV
Fig.11 Write to GPIO port
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2009.09 - Rev.A
BU1850MUV
Technical Note
4-4 Read from GPIO port After writing of the Slave address and R/W bits, reading GPIO port is begun from the following byte. The data that had been being fixed between the following Acknowledge after Acknowledge is taken into the GPI register, and it is transmitted to Master. All ports that are the input by WRSEL register are read to the GPI register according to the timing of Read Configuration Pulse. Therefore, the data of each bit that SDA transmits is the GPI register value taken immediately before that.
SCL
1
2
3
4
5
6
7
8
9
SDA
S
X
X
X
X
X
X
X
1
Ack
D1 [7]
D1 [6]
D1 [5]
D1 [4]
D2 [3]
D2 [2]
D2 [1]
D2 [0]
NA
P
Start Condition Read Configuration Pulse GPI[7:0] Reg
Read
Acknowledge From Slave
Stop Condition No Acknowledge From Master
D1
D2
GPIO[7:0]
D1
D2
tDS
tDH
tDS
tDH
Fig.12 Read from GPIO port
4-5 Interrupt Valid/Reset If GPIO port becomes different from the GPIn register (default is "0"), XINT port is changed from "1" into "0". It becomes "1" to release "0" of XINT port after acknowledge by reading GPI register. Because the value of GPIO port is reflected in the output as it is and is not latched, XINT becomes "1" again if the port returns to the same value. If the ports with INTEN register "1" are different even by one, XINT becomes "0". If it is distinguished which GPIO port changes, it is necessary to keep the GPI register value on the master side and compare with the value that is read after XINT is asserted.
SCL
1
2
3
4
5
6
7
8
9
SDA
S
X
X
X
X
X
X
X
1
Ack
MSB
Data2 (GPI[7:0])
LSB
NA
P
Start Condition
Read
Acknowledge From Slave
Stop Condition No Acknowledge From Master
GPIOn
Data1
Data2
Data3
Data2
GPIn Reg
Data1
Data2
XINT
tIV
tIR
tIV
tIR
Fig.13 Interrupt Valid/Reset
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Electrical Specification 1. DC characteristics VVDD=1.8VVVDDIO=1.8VTopr=25
Technical Note
Specification Parameter Input H Voltage1 Input L Voltage1 Input H Voltage2 Input L Voltage2 Input H Voltage3 Input H Current1 (3V Tolerant) Input H Current2 Input L Current Output H Voltage1 Output L Voltage1 Output H Voltage2 Output L Voltage2 Output L Voltage3 Symbol Min VIH1 VIL1 VIH2 VIL2 VIH3 IIH1 IIH2 IIL VOH1 VOL1 VOH2 VOL2 VOL3
0.7xVVDDIO
Unit Typ Max 3.6
0.3xVVDDIO
Conditions
V GPIO[7:0] V V V V
A A A
-0.2
0.7xVVDD
3.6
0.3xVVDD VVDD+0.2
SCL, SDA, SCL, SDA, XRST, ADR XRST, ADR VIN=3.6V*1 VIN=1.8V, XRST,ADR VIN=0V*1, XRST,ADR IOH=-2mA, GPIO[7:0] IOL=2mA, GPIO[7:0] IOH=-0.2mA, GPIO[7:0] IOL=0.2mA, GPIO[7:0] IOL=3mA, SDA, XINT
-0.2
0.7xVVDD
-1 -1 -1
0.75xVVDDIO
1 1 1 0.25xVVDDIO
V V V V V
VVDDIO-0.25
0.25 0.3
-
*1 XINT(Hi-Z), XRST, SCL, SDA(IN), ADR, GPIO[7:0](IN, Pull-down OFF)
2. Circuit Current VVDD=1.8VVVDDIO=1.8VTopr=25 Specification Parameter Power Down Current (VDD) Power Down Current (VDDIO) Standby Current (VDD) Standby Current (VDDIO) Operating Current1 (VDD) Operating Current1 (VDD)
*1 *2
Symbol Min IPD1 IPD2 ISTBY1 ISTBY2 IOP1 IOP2 Typ 14 2 Max 1.0 1.0 3.0 1.0 25 8
Unit
A A A A A A
Condition
XRST=VSS
XRST=VDD, SCL=VDD, SDA=VDD
I2C 400kHz 100% traffic density*1 I2C 400kHz 1% traffic density*2
All GPIO ports are output, and they repeat 01010101 and 10101010. The period when I2C did not operate was inserted in *1 pattern by 99%.
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3. I2C AC characteristics
State Repeated START BIT 7 BIT 6 Ack STOP
Technical Note
tSU;STA tLOW tHIGH SCL SDA tBUF tHD;STA
1/fSCLK
tSU;DAT tHD;DAT Fig.14 I2C AC Timing
tSU;STO
VVDD=1.8VVVDDIO=1.8VTopr=25 Specification Parameter Symbol Min SCL Clock Frequency Bus free time (Repeated)START Condition Setup Time (Repeated)START Condition Hold Time SCL Low Time SCL High Time Data Setup Time Data Hold Time STOP Condition Setup Time fSCLK tBUF tSU;STA tHD;STA tLOW tHIGH tSU;DAT tHD;DAT tSU;STO 1.3 0.6 0.6 1.3 0.6 100 0 0.6 Typ Max 400 kHz
s s s s s s
Unit
Conditions
ns
s
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4. GPIO AC Characteristics
State BIT 1 BIT 0 Ack BIT 1 BIT 0 Ack
Technical Note
SCL tDV GPIO[7:0](Output) tDS GPIO[7:0](Input) tIV XINT tIR tDH
Fig.15 GPIO AC timing VVDD=1.8VVVDDIO=1.8VTopr=25 Specification Parameter Output Data Valid Time Input Data Setup Time Input Data Hold Time Interrupt Valid Time Interrupt Reset Time Symbol Min tDV tDS tDH tIV tIR 100 0.8 Typ Max 0.8 5 5
s
Unit
Conditions See Fig.11
ns See Fig.12
s s
See Fig.13
s
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5. Startup sequence
tVDD VDD, VDDIO tRWAIT XRST tVDD tI2CWAIT SCL tI2CWAIT tVDD
Technical Note
tVDD tRV tRWAIT
SDA
Fig.16 Start Sequence timing VVDD=1.8VVVDDIO=1.8VTopr=25 Specification Parameter VDD Stable Time Reset Wait Time Reset Valid Time I2C Wait Time
*1
Symbol Min tVDD tRWAIT tRV tI2CWAIT 0 10 10 Typ Max 5 -
Unit ms
s s s
Conditions VDD and VDDIO are ON at the same time. XRST controlling *1
Even if XRST port is not used, it operates because Power On Reset is built in. In this case, connect XRST port with VDD on the set PCB.
Note) At VDD=0V, when SCL port is changed from 0V to 0.5V or more, SCL port pulls the current. It is same in SDA, XINT, and GPIO[7:0] ports of 3V tolerant I/O. (VDDIO=0V in case of GPIO[7:0] ports)
VDD
0V
Port (2k Pull-Up) Port Pull Current
3V 0V 0.11mA
23ms
Fig.17 Port operating at VDD=0V
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Application circuit example
Technical Note
1.8V 1.8V 0.1uF 0.1uF 3.0V 0.1uF 0.1uF
VDDIO
XRST
BU1850MUV
IN
XINT
GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
XINT
BU1850MUV
ADR
GPIO7
ADR
XRST
MPU
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
SCL SDA
SCL SDA
SCL SDA
Other I2C Devices
Fig.18 Application circuit example
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VDDIO
VDD
VDD
VSS
VSS
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Ordering part number
Technical Note
B
U
1
Part No.
8
5
0
M
U
V
-
E
2
Part No.
Package MUV: VQFN016V3030
Packaging and forming specification E2: Embossed tape and reel
VQFN016V3030

3.00.1
Tape
3.00.1
Embossed carrier tape 3000pcs E2
The direction is the 1pin of product is at the upper left when you hold
Quantity Direction of feed
1PIN MARK
1.0MAX
S
+0.03 0.02 -0.02 (0.22)
( reel on the left hand and you pull out the tape on the right hand
)
0.08 S 1.40.1 C0.2
0.40.1
1 16 13 12 9 4 5 8
0.5
0.75
+0.05 0.25 -0.04
1.40.1
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
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Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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